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ltc2460/ltc2462 1 24602fa ?50 ?10 10 ?30 50 70 30 90 temperature (c) reference output voltage (v) 1.2520 1.2515 1.2510 1.2505 1.2500 24602 ta01b 1.2480 1.2485 1.2490 1.2495 typical a pplica t ion fea t ures a pplica t ions descrip t ion ultra-tiny, 16-bit ? adcs with 10ppm/c max precision reference the ltc ? 2460/ltc2462 are ultra tiny, 16-bit analog-to- digital converters with an integrated precision reference. they use a single 2.7v to 5.5v supply and communicate through an spi interface. the ltc2460 is single-ended with a 0v to v ref input range and the ltc2462 is dif - ferential with a v ref input range. both adcs include a 1.25v integrated reference with 2ppm/c drift per - formance and 0.1% initial accuracy. the converters are available in a 12-pin dfn 3mm 3mm package or an msop-12 package. they include an integrated oscillator and perform conversions with no latency for multiplexed applications. the ltc2460/ltc2462 include a proprietary input sampling scheme that reduces the average input current several orders of magnitude when compared to conventional delta sigma converters. following a single conversion, the ltc2460/ltc2462 automatically power down the converter and can also be configured to power down the reference. when both the adc and reference are powered down, the supply current is reduced to 200na. the ltc2460/ltc2462 can sample at 60 conversions per second, and due to the very large oversampling ratio, have extremely relaxed antialiasing requirements. both include continuous internal offset and fullscale calibration algorithms which are transparent to the user, ensuring accuracy over time and the operating temperature range. v ref vs temperature n 16-bit resolution, no missing codes n internal reference, high accuracy 10ppm/c (max) n single-ended (ltc2460) or differential (l tc2462) n 2lsb offset error n 0.01% gain error n 60 conversions per second n single conversion settling time for multiplexed applications n single-cycle operation with auto shutdown n 1.5ma supply current n 2a (max) sleep current n internal oscillatorno external components required n spi interface n ultra-tiny 12-lead 3mm 3mm dfn and msop packages n system monitoring n environmental monitoring n direct temperature measurements n instrumentation n industrial process control n data acquisition n embedded adc upgrades 10k 10k 10k r sck spi interface sdo cs 0.1f 0.1f 2.7v to 5.5v 10f 0.1f in + refout ref ? v cc 0.1f comp gnd in ? 0.1f ltc2462 24602 ta01a l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and no latency ? is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 6208279, 6411242, 7088280, 7164378.
ltc2460/ltc2462 2 24602fa p in c on f igura t ion a bsolu t e maxi m u m r a t ings supply voltage (v cc ) ................................... C0 .3v to 6v analog input voltage (in + , in C , in, ref C , comp, refout) ........................... C 0.3v to (v cc + 0.3v) digital voltage (v sdi , v sdo , v sck , v cs ) ................ C0 .3v to (v cc + 0.3v) (notes 1, 2) or d er in f or m a t ion storage temperature range .................. C 65c to 150c operating temperature range ltc2460c/ltc2462c ............................... 0 c to 70c ltc2460i/ltc2462i ............................. C 40c to 85c ltc2462 ltc2462 top view dd package 12-lead (3mm 3mm) plastic dfn 12 11 8 9 10 4 5 3 2 1 v cc gnd in ? in + ref ? gnd refout comp cs sdi sck sdo 6 7 t jmax = 125c, ja = 43c/w exposed pad (pin 13) pcb ground connection optional 1 2 3 4 5 6 refout comp cs sdi sck sdo 12 11 10 9 8 7 v cc gnd in ? in + ref ? gnd top view ms package 12-lead plastic msop t jmax = 125c, ja = 120c/w ltc2460 ltc2460 top view dd package 12-lead (3mm 3mm) plastic dfn 12 11 8 9 10 4 5 3 2 1 v cc gnd gnd in ref ? gnd refout comp cs sdi sck sdo 6 7 t jmax = 125c, ja = 43c/w exposed pad (pin 13) pcb ground connection optional 1 2 3 4 5 6 refout comp cs sdi sck sdo 12 11 10 9 8 7 v cc gnd gnd in ref ? gnd top view ms package 12-lead plastic msop t jmax = 125c, ja = 120c/w lead free finish tape and reel part marking* package description temperature range ltc2460cdd#pbf ltc2460cdd#trpbf lfdq 12-lead plastic (3mm 3mm) dfn 0c to 70c ltc2460idd#pbf ltc2460idd#trpbf lfdq 12-lead plastic (3mm 3mm) dfn C40c to 85c ltc2460cms#pbf ltc2460cms#trpbf 2460 12-lead plastic msop-12 0c to 70c ltc2460ims#pbf ltc2460ims#trpbf 2460 12-lead plastic msop-12 C40c to 85c ltc2462cdd#pbf ltc2462cdd#trpbf ldxm 12-lead plastic (3mm 3mm) dfn 0c to 70c ltc2462idd#pbf ltc2462idd#trpbf ldxm 12-lead plastic (3mm 3mm) dfn C40c to 85c ltc2462cms#pbf ltc2462cms#trpbf 2462 12-lead plastic msop-12 0c to 70c ltc2462ims#pbf ltc2462ims#trpbf 2462 12-lead plastic msop-12 C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc2460/ltc2462 3 24602fa e lec t rical c harac t eris t ics parameter conditions min typ max units resolution (no missing codes) (note 3) l 16 bits integral nonlinearity (note 4) l 1 10 lsb offset error l 2 15 lsb offset error drift 0.02 lsb/c gain error includes contributions of adc and internal reference l 0.01 0.25 % of fs gain error drift includes contributions of adc and internal reference c-grade i-grade l l 2 5 10 ppm/c ppm/c transition noise 2.2 v rms power supply rejection dc 80 db the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 2) a nalog i npu t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion nap sleep l l l 1.5 800 0.2 2.5 1500 2 ma a a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. symbol parameter conditions min typ max units v in + positive input voltage range ltc2462 l 0 v ref v v in C negative input voltage range ltc2462 l 0 v ref v v in input voltage range ltc2460 l 0 v ref v v or + , v ur + overrange/underrange voltage, in + v in C = 0.625v (see figure 3) 8 lsb v or C , v ur C overrange/underrange voltage, inC v in + = 0.625v (see figure 3) 8 lsb c in in + , in C , in sampling capacitance 0.35 pf i dc_leak(in + , in C , in) in + , in C dc leakage current (ltc2462) in dc leakage current (ltc2460) v in = gnd (note 8) v in = v cc (note 8) l l C10 C10 1 1 10 10 na na i dc_leak(in C ) in C dc leakage current v in = gnd (note 8) v in = v cc (note 8) l l C10 C10 1 1 10 10 na na i conv input sampling current (note 5) 50 na v ref reference output voltage l 1.247 1.25 1.253 v reference voltage coefficient (note 11) c-grade i-grade l 2 5 10 ppm/c ppm/c reference line regulation 2.7v v cc 5.5v C90 db reference short circuit current v cc = 5.5, forcing output to gnd l 35 ma comp pin short circuit current v cc = 5.5, forcing output to gnd l 200 a reference load regulation 2.7v v cc 5.5v, i out = 100a sourcing 3.5 mv/ma reference output noise density c comp = 0.1f, c refout = 0.1f, at f = 1khz 30 nv/ hz p ower r equire m en t s
ltc2460/ltc2462 4 24602fa the l denotes the specifications which apply over the full operating temperature range,otherwise specifications are at t a = 25c. symbol parameter conditions min typ max units t conv conversion time l 13 16.6 23 ms f sck sck frequency range l 2 mhz t lsck sck low period l 250 ns t hsck sck high period l 250 ns t 1 cs falling edge to sdo low z (notes 7, 8) l 0 100 ns t 2 cs rising edge to sdo high z (notes 7, 8) l 0 100 ns t 3 cs falling edge to sck falling edge l 100 ns t kq sck falling edge to sdo valid (note 7) l 0 100 ns t 4 sdi setup before sck (note 3) l 100 ns t 5 sdi hold after sck (note 3) l 100 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. all voltage values are with respect to gnd. v cc = 2.7v to 5.5v unless otherwise specified. v refcm = v ref /2, fs = v ref v in = v in + C v in C , Cv ref v in v ref ; v incm = (v in + + v in C )/2. note 3. guaranteed by design, not subject to test. note 4. integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. guaranteed by design and test correlation. note 5: cs = v cc . a positive current is flowing into the dut pin. note 6: sck = v cc or gnd. sdo is high impedance. note 7: see figure 4. note 8: see figure 5. note 9: input sampling current is the average input current drawn from the input sampling network while the ltc2460/ltc2462 is actively sampling the input. note 10: a positive current is flowing into the dut pin. note 11: temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. ti m ing c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range,otherwise specifications are at t a = 25c. (note 2) symbol parameter conditions min typ max units v ih high level input voltage l v cc C 0.3 v v il low level input voltage l 0.3 v i in digital input current l C10 10 a c in digital input capacitance 10 pf v oh high level output voltage i o = C800a l v cc C 0.5 v v ol low level output voltage i o = 1.6ma l 0.4 v i oz hi-z output leakage current l C10 10 a digi t al i npu t s an d digi t al o u t pu t s
ltc2460/ltc2462 5 24602fa typical p er f or m ance c harac t eris t ics offset error vs temperature adc gain error vs temperature transition noise vs temperature conversion mode power supply current vs temperature sleep mode power supply current vs temperature v ref vs temperature (t a = 25c, unless otherwise noted) temperature (c) offset error (lsb) 1 5 24602 g04 ?1 0 2 3 4 ?2 ?3 ?4 ?5 v cc = 5.5v v cc = 4.1v v cc = 2.7v ?50 ?10 10 ?30 50 70 30 90 temperature (c) ?50 adc gain error (lsb) 25 5 24602 g05 0 15 10 20 ?25 25 50 75 0 100 v cc = 5.5v v cc = 4.1v v cc = 2.7v temperature (c) transition noise rms (v) 6 10 24602 g06 4 5 7 8 9 3 2 1 0 ?50 ?10 10 ?30 50 70 30 90 v cc = 5.5v v cc = 2.7v ?50 ?10 10 ?30 50 70 30 90 v cc = 5.5v v cc = 2.7v temperature (c) conversion current (ma) 2.0 1.9 24602 g07 1.4 1.5 1.6 1.7 1.8 1.3 1.2 1.1 1.0 v cc = 4.1v ?50 ?10 10 ?30 50 70 30 90 v cc = 5.5v v cc = 2.7v v cc = 4.1v temperature (c) sleep current (na) 350 24602 g08 150 300 250 200 100 50 0 ?50 ?10 10 ?30 50 70 30 90 temperature (c) reference output voltage (v) 1.2508 24602 g09 1.2502 1.2503 1.2504 1.2505 1.2506 1.2507 integral nonlinearity integral nonlinearity maximum inl vs temperature differential input voltage (v) ?1.25 ?0.75 ?0.25 inl (lsb) 1 3 24602 g02 ?1 0 2 ?2 ?3 0.25 0.75 1.25 v cc = 2.7v t a = ?45c, 25c, 90c temperature (c) ?55 inl (lsb) 1 3 24602 g03 ?1 0 2 ?2 ?3 ?35 ?15 25 45 65 85 5 125105 v cc = 5.5v, 4.1v, 2.7v differential input voltage (v) ?1.25 ?0.75 ?0.25 inl (lsb) 1 3 24602 g01 ?1 0 2 ?2 ?3 0.25 0.75 1.25 v cc = 5.5v t a = ?45c, 25c, 90c
ltc2460/ltc2462 6 24602fa p in func t ions refout (pin 1): reference output pin. nominally 1.25v, this voltage sets the fullscale input range of the adc. for noise and reference stability connect to a 0.1f capacitor tied to gnd. this capacitor value must be less than or equal to the capacitor tied to the reference compensation pin (comp). refout cannot be overdriven by an external reference. for applications that require an input range greater than 0v to 1.25v, please refer to the ltc2450/ ltc2452. comp (pin 2): internal reference compensation pin. for low noise and reference stability, tie a 0.1f capacitor to gnd. cs (pin 3): chip select (active low) digital input. a low on this pin enables the sdo output. a high on this pin places the sdo output pin in a high impedance state and any inputs on sdi and sck will be ignored. sdi (pin 4): serial data input pin. this pin is used to pro- gram the sleep mode and 30hz/60hz output rate (ltc2460). sck (pin 5): serial clock input. sck synchronizes the serial data input/output. once the conversion is complete, a new data bit is produced at the sdo pin following each sck falling edge. data is shifted into the sdi pin on each rising edge of sck. sdo (pin 6): three-state serial data output. sdo is used for serial data output during the data input/output state and can be used to monitor the conversion status. gnd (pins 7, 11): ground. connect directly to the ground plane through a low impedance connection. ref C (pin 8): negative reference input to the adc. the voltage on this pin sets the zero input to the adc. this pin should tie directly to ground or the ground sense of the input sensor. in + (ltc2462), in (ltc2460) (pin 9): positive input volt- age for the ltc2462 differential device. adc input for the ltc2460 single-ended device. in C (ltc2462), gnd (ltc2460) (pin 10): negative input voltage for the ltc2462 differential device. gnd for the ltc2460 single-ended device. v cc (pin 12): positive supply voltage. bypass to gnd with a 10f capacitor in parallel with a low-series-inductance 0.1f capacitor located as close to the device as possible. exposed pad (pin 13 C dfn package): ground. connect directly to the ground plane through a low impedance connection. typical p er f or m ance c harac t eris t ics (t a = 25c, unless otherwise noted) power supply rejection vs frequency at v cc conversion time vs temperature frequency at v cc (hz) 1 rejection (db) 0 24602 g10 ?20 ?40 ?60 ?80 ?100 ?120 10 1k 10k 100k 1m 100 10m temperature (c) ?50 conversion time (ms) 21 24602 g11 20 16 17 18 19 15 14 ?25 25 50 75 0 100 v cc = 5v, 4.1v, 3v v ref vs v cc 2.0 3.5 2.5 4.0 3.0 5.0 5.5 4.5 6.0 v cc (v) v ref (v) 1.24892 1.24891 24602 g12 1.24884 1.24885 1.24886 1.24887 1.24888 1.24889 1.24890 t a = 25c
ltc2460/ltc2462 7 24602fa a pplica t ions i n f or m a t ion c onverter o peration converter operation cycle the ltc2460/l tc2462 are low power, delta sigma, ana - log to digital converters with a simple spi interface (see figure 1). the ltc2462 has a fully differential input while the ltc2460 is single-ended. both are pin and software compatible. their operation is composed of three distinct states: convert, sleep/nap, and data input/output. the operation begins with the convert state (see fig - ure 2). once the conversion is finished, the converter automatically powers down (nap) or under user control, both the converter and reference are powered down (sleep). the conversion result is held in a static register while the device is in this state. the cycle concludes with the data input/output state. once all 16-bits are read or an abort is initiated the device begins a new conversion. the convert state duration is determined by the ltc2460/ ltc2462 conversion time (nominally 16.6 milliseconds). once started, this operation can not be aborted except by a low power supply condition (v cc < 2.1v) which generates an internal power-on reset signal. after the completion of a conversion, the ltc2460/ltc2462 enters the sleep/nap state and remains there until the chip select is low (cs = low). following this condition, the adc transitions into the data input/output state. figure 2. ltc2460/ltc2462 state transition diagram while in the sleep/nap state, when chip select input is high (cs = high), the ltc2460/ltc2462s converters are powered down. this reduces the supply current by approximately 50%. while in the nap state the reference remains powered up. in order to power down the reference in addition to the converter, the user can select the sleep data input/output sleep/nap convert power-on reset yes 24602 f02 16th falling edge of sck or cs = high? cs = low? no yes no b lock diagra m figure 1. functional block diagram ? a/d converter decimating sinc filter sdo refout comp ref ? in + (in) in ? (gnd) sck cs 24602 bd ? ? a/d converter internal reference ( ) parenthesis indicate ltc2460 spi interface internal oscillator 1 v cc 12 2 3 5 6 sdi 4 8 gnd 7,11,13 (dd package) 9 10
ltc2460/ltc2462 8 24602fa applica t ions in f or m a t ion mode during the data input/output state. once the next conversion is complete, the sleep state is entered and power is reduced to less than 2a. the reference is powered up once cs is brought low. the reference startup time is 12ms (if the reference and compensation capacitor values are both 0.1f). upon entering the data input/output state, sdo outputs the sign (d15) of the conversion result. during this state, the adc shifts the conversion result serially through the sdo output pin under the control of the sck input pin. there is no latency in generating this data and the result corresponds to the last completed conversion. a new bit of data appears at the sdo pin following each falling edge detected at the sck input pin and appears from msb to lsb. the user can reliably latch this data on every rising edge of the external serial clock signal driving the sck pin. during the data input/output state, the ltc2460/ ltc2462 can be programmed to sleep or nap (default) following the next conversion cycle. data is shifted into the device through the sdi pin on the rising edge of sck. the input word is 4 bits. if the first bit en1 = 1 and the second bit en2 = 0 the device is enabled for programming. the following two bits (spd and slp) will be written into the device. spd (only used for the ltc2460) to select the 60hz output rate, no offset calibration mode (spd = 0, default). set spd = 1 for 30hz mode with offset calibration. spd is ignored for the ltc2462. the next bit (slp) enables the sleep or nap mode. if slp = 0 (default) the reference remains powered up at the end of the next conversion cycle. if slp = 1, the reference powers down following the next conversion cycle. the remaining 12 sdi input bits are ignored (dont care). sdi may also be tied directly to gnd or v dd in order to simplify the user interface. in the case of the ltc2460, the 60hz output rate is selected if sdi is tied low and the 30hz output rate is selected if sdi is tied to v dd . the ltc2462 output rate is always 60hz independent of sdi or spd. the reference sleep mode is disabled for both the ltc2460 and ltc2462 if sdi is tied to gnd or v dd . the data input/output state concludes in one of two different ways. first, the data input/output state opera - tion is completed once all 16 data bits have been shifted out and the clock then goes low. this corresponds to the 16 th falling edge of sck. second, the data input/out - put state can be aborted at any time by a low-to-high transition on the cs input. following either one of these two actions, the ltc2460/ltc2462 will enter the convert state and initiate a new conversion cycle. power-up sequence when the power supply voltage (v cc ) applied to the con- verter is below approximately 2.1v, the adc performs a power-on reset. this feature guarantees the integrity of the conversion result. when v cc rises above this critical threshold, the converter generates an internal power-on reset (por) signal for approximately 0.5ms. the por signal clears all internal registers. following the por signal, the ltc2460/ltc2462 start a conversion cycle and follow the succession of states shown in figure 2. the reference startup time following a por is 12ms (c comp = c refout = 0.1f). the first conver - sion following powerup will be invalid since the reference voltage has not completely settled. the first conversion following power up can be discarded using the data abort command or simply read and ignored. the following con- versions are accurate to the device specifications. ease of use the ltc2460/ltc2462 data output has no latency, filter settling delay or redundant results associated with the conversion cycle. there is a one-to-one correspondence figure 3. output code vs v in + with v in C = 0 (ltc2462) v in + /v ref + ?0.001 output code 4 12 20 0.001 24602 f03 ?4 ?12 0 8 16 ?8 ?16 ?20 ?0.005 0 0.005 0.0015 signals below gnd
ltc2460/ltc2462 9 24602fa between the conversion and the output data. therefore, multiplexing multiple analog input voltages requires no special actions. the ltc2460/ltc2462 perform offset calibrations every conversion. this calibration is transparent to the user and has no effect upon the cyclic operation described previously. the advantage of continuous calibration is stability of the adc performance with respect to time and temperature. the ltc2460/ltc2462 include a proprietary input sampling scheme that reduces the average input current by several orders of magnitude when compared to traditional delta- sigma architectures. this allows external filter networks to interface directly to the ltc2460/ltc2462. since the average input sampling current is 50na, an external rc lowpass filter using 1k and 0.1f results in <1lsb additional error. additionally, there is negligible leakage current between in + and in C . input voltage range (ltc2460) ignoring offset and full-scale errors, the ltc2460 will theoretically output an all zero digital result when the input is at ground (a zero scale input) and an all one digital result when the input is at v ref (v refout = 1.25v). in an under-range condition, for all input voltages below zero scale, the converter will generate the output code 0. in an over-range condition, for all input voltages greater than v ref , the converter will generate the output code 65535. for applications that require an input range greater than 0v to 1.25v, please refer to the ltc2450. input voltage range (ltc2462) as mentioned in the output data format section, the output code is given as 32768 ? (v in + C v in C )/v ref + 32768. for (v in + C v in C ) v ref , the output code is clamped at 65535 (all ones). for (v in + C v in C ) Cv ref , the output code is clamped at 0 (all zeroes). the ltc2462 includes a proprietary architecture that can, typically, digitize each input up to 8 lsbs above v ref and below gnd, if the differential input is within v ref . as an example (figure 3), if the user desires to measure a signal slightly below ground, the user could set v in C = gnd, and v ref = 1.25v. if v in + = gnd, the output code would be approximately 32768. if v in + = gnd C 8lsb = C0 .305mv, the output code would be approximately 32760. for applications that require an input range greater than 1.25v, please refer to the ltc2452. output data format the ltc2460/ltc2462 generates a 16-bit direct binary encoded result. it is provided as a 16-bit serial stream through the sdo output pin under the control of the sck input pin (see figure 4). the ltc2462 (differential input) output code is given by 32768 ? (v in + C v in C )/v ref + 32768. the first bit output by the ltc2462, d15, is the msb, which is 1 for v in + v in C and 0 for v in + < v in C . this bit is followed by succes- sively less significant bits (d14, d13, ) until the lsb is output by the ltc2462, see table 1. d 15 lsb sdo sck d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 0 d 1 24602 f04 t 1 t 3 t kq t lsck t hsck t 2 cs msb sdi en2 spd* *spd is a don?t care bit for the ltc2462 slp don?t care t 5 t 6 en1 a pplica t ions i n f or m a t ion figure 4. data input/output timing
ltc2460/ltc2462 10 24602fa applica t ions in f or m a t ion the ltc2460 (single-ended input) output code is a direct binary encoded result, see table 1. during the data output operation the cs input pin must be pulled low (cs = low). the data output process starts with the most significant bit of the result being present at the sdo output pin (sdo = d15) once cs goes low. a new data bit appears at the sdo output pin after each falling edge detected at the sck input pin. the output data can be reliably latched on the rising edge of sck. data input format the data input word is 4 bits long and consists of two en- able bits (en1 and en2) and two programming bits (spd and slp). en1 is applied to the first rising edge of sck after the conversion is complete. programming is enabled by setting en1 = 1 and en2 = 0. the speed bit (spd) is only used by the ltc2460. in the default mode, spd = 0, the output rate is 60hz and con- tinuous background offset calibration is not performed. by changing the spd bit to 1, background offset calibration is performed and the output rate is reduced to 30hz. alterna - tively, sdi can be tied directly to ground (spd = 0) or v cc (spd = 1), eliminating the need to program the device. the ltc2462 data output rate is always 60hz and background offset calibration is performed (spd = dont care). the sleep bit (slp) is used to power down the on chip reference. in the default mode, the reference remains powered up even when the adc is powered down. if the slp bit is set high, the reference will power down after the next conversion is complete. it will remain powered down until cs is pulled low. the reference startup time is approximately 12ms. in order to ensure a stable refer - ence for the following conversions, either the data input/ output time should be delayed 12ms after cs goes low or the first conversion following a reference start up should be discarded. if sdi is tied high (ltc2460 operating in 30hz mode) the slp mode is disabled. conversion status monitor for certain applications, the user may wish to monitor the ltc2460/ltc2462 conversion status. this can be achieved by holding sck high during the conversion cycle. in this condition, whenever the cs input pin is pulled low (cs = low), the sdo output pin will provide an indication of the conversion status. sdo = high is an indication of a conversion cycle in progress while sdo = low is an indication of a completed conversion cycle. an example of such a sequence is shown in figure 5. conversion status monitoring, while possible, is not re- quired for the ltc2460/ltc2462 as its conversion time is fixed and typically 16.6ms (23ms maximum). therefore, external timing can be used to determine the completion of a conversion cycle. s erial i nterf ace the ltc2460/l tc2462 transmit the conversion result and receive the start of conversion command through a syn- chronous 2-, 3- or 4-wire interface. this interface can be table 1. ltc2460/ltc2462 output data format single ended input v in (ltc2460) differential input voltage v in + C v in C (ltc2462) d15 (msb) d14 d13 d12...d2 d1 d0 (lsb) corresponding decimal value v ref v ref 1 1 1 1 1 1 65535 v ref C 1lsb v ref C 1lsb 1 1 1 1 1 0 65534 0.75 ? v ref 0.5 ? v ref 1 1 0 0 0 0 49152 0.75 ? v ref C 1lsb 0.5 ? v ref C 1lsb 1 0 1 1 1 1 49151 0.5 ? v ref 0 1 0 0 0 0 0 32768 0.5 ? v ref C 1lsb C1lsb 0 1 1 1 1 1 32767 0.25 ? v ref C0.5 ? v ref 0 1 0 0 0 0 16384 0.25 ? v ref C 1lsb C0.5 ? v ref C 1lsb 0 0 1 1 1 1 16383 0 Cv ref 0 0 0 0 0 0 0
ltc2460/ltc2462 11 24602fa a pplica t ions i n f or m a t ion used during the convert and sleep states to assess the conversion status and during the data output state to read the conversion result, and to trigger a new conversion. serial interface operation modes the modes of operation can be summarized as follows: 1) the ltc2460/l tc2462 function with sck idle high (commonly known as cpol = 1) or idle low (commonly known as cpol = 0). 2) after the 16th bit is read, a new conversion is started if cs is pulled high or sck is pulled low. 3) at any time during the data output state, pulling cs high causes the part to leave the i/o state, abort the output and begin a new conversion. 4) when sck = high, it is possible to monitor the conver - sion status by pulling cs low and watching for sdo to go low . this feature is available only in the idle-high (cpol = 1) mode. serial clock idle-high (cpol = 1) examples in figure 6, following a conversion cycle the ltc2460/ ltc2462 automatically enter the nap mode with the adc powered down. the adcs reference will power down if the slp bit was set high prior to the just completed conversion and cs is high. once cs goes low, the device powers up. the user can monitor the conversion status at convenient intervals using cs and sdo. pulling cs low while sck is high tests whether or not the chip is in the convert state. while in the convert state, sdo is high while cs is low. once the conversion is complete, sdo is low figure 5. conversion status monitoring mode nap t 1 t 2 sdo sck = high sdi = low convert 24602 f05 cs figure 6. idle-high (cpol = 1) serial clock operation example. the rising edge of cs starts a new conversion d 15 clk 1 clk 2 clk 3 clk 4 clk 15 clk 16 d 14 d 13 d 12 d 2 d 1 d 0 sd0 sck convert convert nap data output 24602 f06 cs sdi en2 spd slp en1
ltc2460/ltc2462 12 24602fa while cs is low. these tests are not required op - erational steps but may be useful for some applications. when the data is available, the user applies 16 clock cycles to transfer the result. the cs rising edge is then used to initiate a new conversion. the operation example of figure 7 is identical to that of figure 6, except the new conversion cycle is triggered by the falling edge of the serial clock (sck). serial clock idle-low (cpol = 0) examples in figure 8, following a conversion cycle the ltc2460/ ltc2462 automatically enters the nap state. the device reference will power down if the slp bit was set high prior to the just completed conversion and cs is high. once cs goes low, the reference powers up. the user determines data availability (and the end of conversion) based upon external timing. the user then pulls cs low (cs = ) and uses 16 clock cycles to transfer the result. following the 16th rising edge of the clock, cs is pulled high (cs = ), which triggers a new conversion. the timing diagram in figure 9 is identical to that of figure 8, except in this case a new conversion is triggered by sck. the 16th sck falling edge triggers a new conversion cycle and the cs signal is subsequently pulled high. examples of aborting cycle using cs for some applications, the user may wish to abort the i/o cycle and begin a new conversion. if the ltc2460/ltc2462 are in the data output state, a cs rising edge clears the remaining data bits from the output register, aborts the out - put cycle and triggers a new conversion. figure 10 shows an example of aborting an i/o with idle-high (cpol = 1) and figure 11 shows an example of aborting an i/o with idle-low (cpol = 0). a new conversion cycle can be triggered using the cs signal without having to generate any serial clock pulses as shown in figure 12. if sck is maintained at a low logic level, after the end of a conversion cycle, a new conver - sion operation can be triggered by pulling cs low and then high. when cs is pulled low (cs = low), sdo will a pplica t ions i n f or m a t ion figure 8. idle-low (cpol = 0) clock. cs triggers a new conversion d 15 d 14 d 13 d 12 d 2 d 1 d 0 clk 1 clk 2 clk 3 clk 4 clk 14 clk 15 clk 16 sck sd0 convert convert nap data output 24602 f08 cs sdi en2 spd slp en1 figure 7. idle-high (cpol = 1) clock operation example. a 17th clock pulse is used to trigger a new conversion cycle d 15 d 14 d 13 d 12 d 2 d 1 d 0 sd0 clk 1 clk 2 clk 3 clk 4 clk 15 clk 16 clk 17 sck convert convert nap data output 24602 f07 cs sdi en2 spd slp en1
ltc2460/ltc2462 13 24602fa applica t ions in f or m a t ion figure 11. idle-low (cpol = 0) clock and aborted i/o example figure 12. idle-low (cpol = 0) clock and minimum data output length example figure 10. idle-high (cpol = 1) clock and aborted i/o example d 15 d 14 d 13 clk 1 clk 2 clk 4 clk 3 convert convert nap data output 24602 f10 sd0 sck cs sdi en2 spd en1 slp d 15 d 14 d 13 sd0 clk 1 clk 2 clk 3 sck convert convert nap data output 24602 f11 cs sdi en2 spd en1 slp sck = low sd0 convert convert nap data output 24602 f12 d 15 cs sdi = don?t care figure 9. idle-low (cpol = 0) clock. the 16th sck falling edge triggers a new conversion d 15 d 14 d 13 d 12 d 2 d 1 d 0 sd0 clk 1 clk 2 clk 3 clk 4 clk 15 clk 14 clk 16 sck convert convert nap data output 24602 f09 cs sdi en2 spd slp en1
ltc2460/ltc2462 14 24602fa applica t ions in f or m a t ion output the sign (d15) of the result of the just completed conversion. while a low logic level is maintained at sck pin and cs is subsequently pulled high (cs = high) the remaining 15 bits of the result (d14:d0) are discarded and a new conversion cycle starts. following the aborted i/o, additional clock pulses in the convert state are acceptable, but excessive signal tran - sitions on sck can potentially create noise on the adc during the conversion, and thus may negatively influence the conversion accuracy. 2-wire operation the 2-wire operation modes, while reducing the number of required control signals, should be used only if the ltc2460/ ltc2462 low power sleep capability is not required. in ad - dition the option to abort serial data transfers is no longer available. hardwire cs to gnd for 2-wire operation. for the ltc2460, tie sdi low for 60hz output rate and high for 30hz output rate, for the ltc2462 tie sdi low. figure 13 shows a 2-wire operation sequence which uses an idle-high (cpol = 1) serial clock signal. the conversion status can be monitored at the sdo output. following a conversion cycle, the adc enters the data output state and the sdo output transitions from high to low. sub - sequently 16 clock pulses are applied to the sck input in order to serially shift the 16 bit result. finally, the 17th clock pulse is applied to the sck input in order to trigger a new conversion cycle. figure 14 shows a 2-wire operation sequence which uses an idle-low (cpol = 0) serial clock signal. the conversion status cannot be monitored at the sdo output. following a conversion cycle, the ltc2460/ltc2462 enters the data output state. at this moment the sdo pin outputs the sign (d15) of the conversion result. the user must use external timing in order to determine the end of conversion and result availability. subsequently 16 clock pulses are applied to sck in order to serially shift the 16-bit result. the 16th clock falling edge triggers a new conversion cycle. for the ltc2460 tie sdi low for 60hz output rate and high for 30hz output rate. figure 13. 2-wire, idle-high (cpol = 1) serial clock, operation example figure 14. 2-wire, idle-low (cpol = 0) serial clock operation example 24602 f13 d 15 d 14 d 13 d 12 d 2 d 1 d 0 sd0 clk 1 clk 2 clk 3 clk 4 clk 15 clk 16 clk 17 sck convert sdi = 0 or 1 convert data output cs = low 24602 f14 d 15 d 14 d 13 d 12 d 2 d 1 d 0 sd0 cs = low clk 1 clk 2 clk 3 clk 14 clk 4 clk 15 clk 16 sck convert convert data output sdi = 0 or 1
ltc2460/ltc2462 15 24602fa a pplica t ions i n f or m a t ion preserving the converter accuracy the ltc2460/ltc2462 are designed to minimize the conver - sion results sensitivity to device decoupling, pcb layout, antialiasing circuits, line and frequency perturbations. nevertheless, in order to preserve the high accuracy capa - bility of this part, some simple precautions are desirable. digital signal levels due to the nature of cmos logic, it is advisable to keep input digital signals near gnd or v cc . voltages in the range of 0.5v to v cc C 0.5v may result in additional current leakage from the part. undershoot and overshoot should also be minimized, particularly while the chip is converting. it is thus beneficial to keep edge rates of about 10ns and limit overshoot and undershoot to less than 0.3v. noisy external circuitry can potentially impact the output under 2-wire operation. in particular, it is possible to get the ltc2460/ltc2462 into an unknown state if an sck pulse is missed or noise triggers an extra sck pulse. in this situation, it is impossible to distinguish sdo = 1 (indicating conversion in progress) from valid 1 data bits. as such, cpol = 1 is recommended for the 2-wire mode. the user should look for sdo = 0 before reading data, and look for sdo = 1 after reading data. if sdo does not return a 0 within the maximum conversion time (or return a 1 after a full data read), generate 16 sck pulses to force a new conversion. driving v cc and gnd in relation to the v cc and gnd pins, the ltc2460/ltc2462 combines internal high frequency decoupling with damping elements, which reduce the adc performance sensitivity to pcb layout and external components. nevertheless, the very high accuracy of this converter is best pre - served by careful low and high frequency power supply decoupling. a 0.1f, high quality, ceramic capacitor in parallel with a 10f low esr ceramic capacitor should be connected between the v cc and gnd pins, as close as possible to the package. the 0.1f capacitor should be placed closest to the adc package. it is also desirable to avoid any via in the circuit path, starting from the converter v cc pin, passing through these two decoupling capacitors, and returning to the converter gnd pin. the area encompassed by this circuit path, as well as the path length, should be minimized. as shown in figure 15, ref C is used as the negative refer - ence voltage input to the adc. this pin can be tied directly to ground or kelvined to sensor ground. in the case where ref C is used as a sense input, it should be bypassed to ground with a 0.1f ceramic capacitor in parallel with a 10f low esr ceramic capacitor. very low impedance ground and power planes, and star connections at both v cc and gnd pins, are preferable. the v cc pin should have two distinct connections: the first to the decoupling capacitors described above, and the second to the ground return for the power supply voltage source. refout and comp the on chip 1.25v reference is internally tied to the con- verters reference input and is output to the refout pin. a 0.1f capacitor should be placed on the refout pin. it is possible to reduce this capacitor, but the transition figure 15. ltc2460/ltc2462 analog input/reference equivalent circuit r sw 15k (typ) i leak i leak v cc v cc v cc v cc c eq 0.35pf (typ) in + in ? ref ? refout internal reference 24602 f15 r sw 15k (typ) i leak i leak r sw 15k (typ) i leak i leak r sw 15k (typ) i leak i leak
ltc2460/ltc2462 16 24602fa applica t ions in f or m a t ion noise increases. a 0.1f capacitor should also be placed on the comp pin. this pin is tied to an internal point in the reference and is used for stability. in order for the refer - ence to remain stable the capacitor placed on the comp pin must be greater than or equal to the capacitor tied to the refout pin. the refout pin cannot be overridden by an external voltage. if a reference voltage greater than 1.25v is required, the ltc2450/ltc2452 should be used. depending on the size of the capacitors tied to the refout and comp pins, the internal reference has a correspond- ing start up time. this start up time is typically 12ms when 0.1f capacitors are used. at initial power up, the first conversion result can be aborted or ignored. at the completion of this first conversion, the reference has settled and all subsequent conversions are valid. if the reference is put to sleep (program slp = 1 and cs = 1) the reference is powered down after the next conversion. this conversion result is valid. on cs falling edge, the reference is powered up. in order to ensure the reference output has settled before the next conversion, the power up time can be extended by delaying the data read 12ms after the falling edge of cs . once all 16 bits are read from the device or cs is brought high, the next conversion automatically begins. in the default operation, the reference remains powered up at the conclusion of the conversion cycle. driving v in + and v in C the input drive requirements can best be analyzed using the equivalent circuit of figure 16. the input signal v sig is connected to the adc input pins (in + and in C ) through an equivalent source resistance r s . this resistor includes both the actual generator source resistance and any additional optional resistors connected to the input pins. optional input capacitors c in are also connected to the adc input pins. this capacitor is placed in parallel with the adc input parasitic capacitance c par . depending on the pcb layout, c par has typical values between 2pf and 15pf. in addition, the equivalent circuit of figure 16 includes the converter equivalent internal resistor r sw and sampling capacitor c eq . figure 16. ltc2460/ltc2462 input drive equivalent circuit i leak i leak r sw 15k (typ) i conv c in in + (ltc2462) in (ltc2460) v cc sig + sig ? r s c eq 0.35pf (typ) c par + ? 24602 f16 i leak i leak r sw 15k (typ) i conv c in in ? (ltc2462) v cc r s c eq 0.35pf (typ) c par + ? there are some immediate trade-offs in r s and c in without needing a full circuit analysis. increasing r s and c in can give the following benefits: 1) due to the ltc2460/l tc2462s input sampling algorithm, the input current drawn by either v in + or v in C over a conversion cycle is typically 50na. a high r s ? c in at - tenuates the high frequency components of the input current, and r s values up to 1k result in <1lsb error. 2) the bandwidth from v sig is reduced at the input pins (in + , in C or in). this bandwidth reduction isolates the adc from high frequency signals, and as such provides simple antialiasing and input noise reduction. 3) switching transients generated by the adc are attenu- ated before they go back to the signal sour ce. 4) a large c in gives a better ac ground at the input pins, helping reduce reflections back to the signal source. 5) increasing r s protects the adc by limiting the current during an outside-the-rails fault condition.
ltc2460/ltc2462 17 24602fa a pplica t ions i n f or m a t ion there is a limit to how large r s ? c in should be for a given application. increasing r s beyond a given point increases the voltage drop across r s due to the input current, to the point that significant measurement errors exist. additionally, for some applications, increasing the r s ? c in product too much may unacceptably attenuate the signal at frequencies of interest. for most applications, it is desirable to implement c in as a high-quality 0.1f ceramic capacitor and r s 1k. this capacitor should be located as close as possible to the actual v in package pin. furthermore, the area encompassed by this circuit path, as well as the path length, should be minimized. in the case of a 2-wire sensor that is not remotely grounded, it is desirable to split r s and place series resistors in the adc input line as well as in the sensor ground return line, which should be tied to the adc gnd pin using a star connection topology. figure 17 shows the measured ltc2462 inl vs input voltage as a function of r s value with an input capacitor c in = 0.1f. in some cases, r s can be increased above these guidelines. the input current is zero when the adc is either in sleep or i/o modes. thus, if the time constant of the input rc circuit t = r s ? c in , is of the same order of magnitude or longer than the time periods between actual conversions, then one can consider the input current to be reduced correspondingly. these considerations need to be balanced out by the input signal bandwidth. the 3db bandwidth 1/(2pr s c in ). finally, if the recommended choice for c in is unacceptable for the users specific application, an alternate strategy is to eliminate c in and minimize c par and r s . in practical terms, this configuration corresponds to a low impedance sensor directly connected to the adc through minimum length traces. actual applications include current measurements through low value sense resistors, temperature measure- ments, low impedance voltage source monitoring, and so on. the resultant inl vs v in is shown in figure 18. the measurements of figure 18 include a capacitor c par cor - responding to a minimum sized layout pad and a minimum width input trace of about 1 inch length. signal bandwidth, transition noise and noise equivalent input bandwidth the ltc2460/ltc2462 include a sinc 1 type digital filter with the first notch located at f 0 = 60hz. as such, the 3db input signal bandwidth is 26.54hz. the calculated ltc2460/ltc2462 input signal attenuation vs frequency over a wide frequency range is shown in figure 19. the calculated ltc2460/ltc2462 input signal attenuation vs frequency at low frequencies is shown in figure 20. the converter noise level is about 2.2v rms and can be mod- eled by a white noise source connected at the input of a noise-free converter. on a related note, the ltc2462 uses two separate a/d converters to digitize the positive and negative inputs. each of these a/d converters has 2.2v rms transition noise. if one of the input voltages is within this small transition noise band, then the output will fluctuate one bit, regard- less of the value of the other input voltage. if both of the input voltages are within their transition noise bands, the output can fluctuate 2 bits. for a simple system noise analysis, the v in drive circuit can be modeled as a single-pole equivalent circuit character - ized by a pole location f i and a noise spectral density n i . if the converter has an unlimited bandwidth, or at least a bandwidth substantially larger than f i , then the total noise contribution of the external drive circuit would be: v n = n i p / 2 ? f i then, the total system noise level can be estimated as the square root of the sum of (v n 2 ) and the square of the ltc2460/ltc2462 noise floor (~2.2v 2 ).
ltc2460/ltc2462 18 24602fa figure 19. ltc2462 input signal attentuation vs frequency figure 20. ltc2462 input signal attenuation vs frequency (low frequencies) applica t ions in f or m a t ion input signal frequency (mhz) 0 input signal attenuation (db) ?40 0 1.00 1.25 1.50 24602 f19 ?60 ?80 ?20 ?100 2.5 5.0 7.5 input signal frequency (hz) 0 input signal attenuatioin (db) ?20 ?10 0 480 24602 f20 ?30 ?40 ?25 ?15 ?5 ?35 ?45 ?50 12060 240180 360 420 540 300 600 figure 17. measured inl vs input voltage figure 18. measured inl vs input voltage differential input voltage (v) ?1.25 ?0.75 ?0.25 inl (lsb) 1 3 24602 f17 ?1 0 2 ?2 ?3 0.25 0.75 1.25 c in = 0.1f v cc = 5v t a = 25c r s = 10k r s = 1k r s = 0k differential input voltage (v) ?1.25 ?0.75 ?0.25 inl (lsb) 1 3 24602 f18 ?1 0 2 ?2 ?3 0.25 0.75 1.25 c in = 0 v cc = 5v t a = 25c r s = 10k r s = 1k r s = 0k
ltc2460/ltc2462 19 24602fa p ackage descrip t ion dd package 12-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1725 rev a) please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (4 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad and tie bars shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 0.75 0.05 r = 0.115 typ 1 6 12 7 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd12) dfn 0106 rev a recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.23 0.05 0.25 0.05 2.25 ref 2.38 0.05 1.65 0.05 2.10 0.05 0.70 0.05 3.50 0.05 package outline pin 1 notch r = 0.20 or 0.25 45 chamfer 2.38 0.10 2.25 ref 0.45 bsc 0.45 bsc
ltc2460/ltc2462 20 24602fa ms package 12-lead plastic msop (reference ltc dwg # 05-08-1668 rev ?) p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. msop (ms12) 1107 rev ? 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 11 10 9 8 7 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 1 2 3 4 5 6 3.00 0.102 (.118 .004) (note 4) 0.406 0.076 (.016 .003) ref 4.90 0.152 (.193 .006) ms package 12-lead plastic msop (reference ltc dwg # 05-08-1668 rev ?)
ltc2460/ltc2462 21 24602fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 09/11 updated offset error maximum in the electrical characteristics table. 3
ltc2460/ltc2462 22 24602fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax : (408) 434-0507 l www.linear.com linear technology corporation 2009 lt 0911 rev a ? printed in usa r ela t e d p ar t s part number description comments ltc1860/ltc1861 12-bit, 5v, 1-/2-channel 250ksps sar adc in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1860l/ltc1861l 12-bit, 3v, 1-/2-channel 150ksps sar adc 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ltc1864/ltc1865 16-bit, 5v, 1-/2-channel 250ksps sar adc in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1864l/ltc1865l 16-bit, 3v, 1-/2-channel 150ksps sar adc 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ltc2360 12-bit, 100ksps sar adc 3v supply, 1.5mw at 100ksps, tsot 6-pin/8-pin packages ltc2440 24-bit no latency )8 ? adc 200nv rms noise, 4khz output rate, 15ppm inl ltc2480 16-bit, differential input, no latency )8 adc, with pga, t emp. sensor, spi easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2481 16-bit, differential input, no latency )8 adc, with pga, t emp. sensor, i 2 c easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2482 16-bit, differential input, no latency )8 adc, spi easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2483 16-bit, differential input, no latency )8 adc, i 2 c easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2484 24-bit, differential input, no latency )8 adc, spi with t emp. sensor easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2485 24-bit, differential input, no latency )8 adc, i 2 c with temp. sensor easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc6241 dual, 18mhz, low noise, rail-to-rail op amp 550nv p-p noise, 125v offset max ltc2450 easy-to-use, ultra-tiny 16-bit adc, spi, 0v to 5.5v input range 2 lsb inl, 50na sleep current, tiny 2mm w 2mm dfn-6 package, 30hz output rate ltc2450-1 easy-to-use, ultra-tiny 16-bit adc, spi, 0v to 5.5v input range 2 lsb inl, 50na sleep current, tiny 2mm w 2mm dfn-6 package, 60hz output rate ltc2451 easy-to-use, ultra-tiny 16-bit adc, i 2 c, 0v to 5.5v input range 2 lsb inl, 50na sleep current, tiny 3mm w 2mm dfn-8 or tsot package, programmable 30hz/60hz output rates ltc2452 easy-to-use, ultra-tiny 16-bit differential adc, spi, 5.5v input range 2 lsb inl, 50na sleep current, tiny 3mm w 2mm dfn-8 or tsot package ltc2453 easy-to-use, ultra-tiny 16-bit differential adc, i 2 c, 5.5v input range 2 lsb inl, 50na sleep current, tiny 3mm w 2mm dfn-8 or tsot package 0.1f v cc in + in ? 24602 ta02 10f 0.1f 7, 118 121 0.1f 0.1f 0.1f 1k 1k 9 10 6 5 3 10v 5v cs sck/scl mosi/sda miso/sdo gnd gnd gnd 1 2 6 4 7 5 1f v cc v + 1383 c cs sck sdo u1* in + refout ref ? v cc gnd 2 comp in ? ltc2462 cs sck sdo 4 sdi 0.1f typical a pplica t ion

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